Please note that this evaluation is based on the average score for each reviewer in all the criteria

• Number of reviewers: 1

Graphs

<aside> 💡 Short Description of the course Material

Introduction to information representation, Signals, and bits, Logic implementation using discrete logic components (TTL, CMOS). Introduction to Field Programmable Logic Arrays (FPGAs) design flow: design capture (schematic capture, HDL design entry, design verification, and test, implementation (including some of its practical aspects), and debugging. Use of CAD tools to design, simulate, and implement digital logic circuits on FPGA prototyping boards. Introduction to Verilog.

Co-Requisite: COE 202

</aside>

General Evaluation

• Difficulty of the course : 3/5 (Normal)
• Is there a Lab for this course: Yes
• is there a project for this course: Yes
• Are there assignments for this course: No
• Is there are any other requirements? (Things that are required from students apart from assignments and projects): No
• in your opinion, How important is the course content for other courses in the plan? : 3/5 (Important)

Detailed Evaluation